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hyb 39s16160ct-5.5/-6/-7 16-mbit synchronous dram data book 1 09.99 the hyb 39s16160ct-5.5/-6/-7 are high-speed dual-bank synchronous drams organized as 2banks 512 kbit 16. these synchronous devices achieve high-speed data transfer rates up to 183 mhz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. the chip is fabricated using the infineon advanced 16 mbit dram process technology. the device is designed to comply with all jedec standards set for synchronous dram products, both electrically and mechanically. all of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. operating the two memory banks in an interleaved fashion allows random access operation to occur at higher rates than is possible with standard drams. a sequential and gapless data rate of up to 183 mhz is possible depending on burst length, cas latency and speed grade of the device. auto refresh (cbr) and self refresh operation are supported. these devices operate with a single 3.3 v 0.3 v power supply and are available in tsopii packages. ? high performance: ? fully synchronous to positive clock edge ? 0 to 70 c operating temperature ? dual banks controlled by a11 (bank select) ? programmable cas latency: 2, 3 ? programmable wrap sequence: sequential or interleave ? programmable burst length: 1, 2, 4, 8 ? full page (optional) for sequential wrap around ? multiple burst read with single write operation ? automatic and controlled precharge command ? data mask for read/write control ? dual data mask for byte control (x16) ? auto refresh (cbr) and self refresh ? suspend mode and power down mode ? 4096 refresh cycles/64 ms ? latency 2 at 133 mhz ? latency 3 at 183 mhz ? random column address every clk (1-n rule) ? single 3.3 v 0.3 v power supply ? lvttl interface ? plastic packages: p-tsopii-50 400 mil width (x16) -5.5 -6 -7 unit f ckmax @ cl = 3 183 166 143 mhz t ck3 5.567ns t ac3 4.555ns f ckmax @ cl = 2 133 125 115 mhz t ck2 7.589ns t ac2 5.466ns 1m 16-mbit synchronous dram for high-speed graphics applications
hyb 39s16160ct-5.5/-6/-7 16-mbit synchronous dram data book 2 09.99 ordering information type ordering code package description lvttl-version hyb 39s16160ct-5.5 on request p-tsopii-50 (400mil) 183 mhz 2b 512k x16 sdram hyb 39s16160ct-6 on request p-tsopii-50 (400mil) 166 mhz 2b 512k x16 sdram hyb 39s16160ct-7 on request p-tsopii-50 (400mil) 143 mhz 2b 512k x16 sdram pin definitions and functions clk clock input dq data input/output cke clock enable ldqm, udqm data mask cs chip select v dd power (+ 3.3 v) ras row address strobe v ss ground cas column address strobe v ddq power for dqs (+ 3.3 v) we write enable v ssq ground for dqs a0 - a10 address inputs n.c. not connected a11(bs) bank select
hyb 39s16160ct-5.5/-6/-7 16-mbit synchronous dram data book 3 09.99 pin configuration spp04117 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 n.c. 27 26 v ss v ss a4 a5 a6 a7 a8 a9 v ddq dq8 cke clk udqm n.c. dq9 v ssq dq10 dq11 v ddq dq13 dq12 v ssq dq15 dq14 v dd a3 a2 a1 a0 a10 a11 cs ras cas we ldqm v ddq dq7 dq6 v ssq dq5 dq4 v ddq dq3 dq2 v ssq dq1 dq0 v dd
hyb 39s16160ct-5.5/-6/-7 16-mbit synchronous dram data book 4 09.99 signal pin description pin type signal polarity function clk input pulse positive edge the system clock input. all of the sdram inputs are sampled on the rising edge of the clock. cke input level active high activates the clk signal when high and deactivates the clk signal when low, thereby inititiates either the power down mode, suspend mode, or the self refresh mode. cs input pulse active low cs enables the command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras , cas , we input pulse active low when sampled at the positive rising edge of the clock, cas , ras , and we define the command to be executed by the sdram. a0 - a10 input level C during a bank activate command cycle, a0-a10 define the row address (ra0 - ra10) when sampled at the rising clock edge. during a read or write command cycle, a0-a9 define the column address (ca0 - can) when sampled at the rising clock edge. can depends on the sdram organization. 1m 16 sdram can = ca7 in addition to the column address, a10 is used to invoke autoprecharge operation at the end of the burst read or write cycle. if a10 is high, autoprecharge is selected and a11 defines the bank to be precharged (low = bank a, high = bank b). if a10 is low, autoprecharge is disabled. during a precharge command cycle, a10 is used in conjunction with a11 to control which bank(s) to precharge. if a10 is high, both bank a and bank b will be precharged regardless of the state of a11. if a10 is low, then a11 is used to define which bank to precharge. a11 (bs) input level C selects which bank is to be active. a11 low selects bank a and a11 high selects bank b. dqx input output level C data input/output pins operate in the same manner as on conventional drams.
hyb 39s16160ct-5.5/-6/-7 16-mbit synchronous dram data book 5 09.99 ldqm, udqm input pulse active high the data input/output mask places the dq buffers in a high impedance state when sampled high. in read mode, dqm has a latency of two clock cycles and controls the output buffers like an output enable. in write mode, dqm has a latency of zero and operates as a word mask by allowing input data to be written if it is low, but blocks the write operation if dqm is high. v dd v ss supply C C power and ground for the input buffers and the core logic. v ddq v ssq supply C C power supply and ground for the output buffers to provide improved noise immunity. signal pin description (contd) pin type signal polarity function
hyb 39s16160ct-5.5/-6/-7 16-mbit synchronous dram data book 6 09.99 functional block diagrams block diagram: hyb 39s16160ct (2 bank 512k 16 sdram) data input / output buffers dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 16 spb04118 address buffers (12) a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11(bs) clk buffer clk cke cke buffer self refresh clock row address counter cs buffer cs ras ras buffer cas cas buffer we we buffer udqm dqm buffer ldqm dqm buffer command decoder bank b row/column select mode register bank a row/column select predecode a predecode b sequential control bank b 16 16 16 12 12 11 11 11 8 sequential control bank a 16 16 3 16 column decoder and dq gate sense amplifiers 2048 x 256 memory bank a row decoder 2048 256 8 data latches column decoder and dq gate sense amplifiers 2048 x 256 memory bank b row decoder data latches 2048 256 8 8
hyb 39s16160ct-5.5/-6/-7 16-mbit synchronous dram data book 7 09.99 operation definition all sdram operations are defined by states of control signals cs , ras , cas , we and dqm at the positive edge of the clock. the following list shows the most important operation commands. mode register for application flexibility, cas latency, burst length, and burst sequence can be programmed in the sdram mode register. the mode set operation must be done after the initial power up and before any activate command . any content of the mode register can be altered by re-executing the mode set command. both banks must be in precharged state and cke must be high at least one clock before the mode set operation. after the mode register is set, a standby or nop command is required. low signals of ras , cas , and we at the positive edge of the clock activate the mode set operation. address input data at this timing defines parameters to be set, as shown in the following table. operation cs ras cas we (l/u)dqm standby, ignore ras , cas , we and addresshxxxx row address strobe and activating a bank l l h h x column address strobe and read command l h l h x column address strobe and write command l h l l x precharge command l l h l x burst stop command l h h l x self refresh entry l l l h x mode register set command llllx write enable/output enable xxxxl write inhibit/output disable xxxxh no operation (nop) l hhhx
hyb 39s16160ct-5.5/-6/-7 16-mbit synchronous dram data book 8 09.99 address input for mode set (mode register operation) spd04119 bs a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 operation mode cas latency bt burst length address bus (ax) mode register (mx) m3 type x x 1 0 0 multiple burst with single write operation mode burst type 1 interleave m5 m4 latency m6 cas latency 0 0 reserved 0 1 0 0 1 2 0 0 1 1 3 1 0 1 0 reserved 0 1 1 0 reserved 0 1 1 1 1 1 m1 m0 length m2 burst length sequential 1 0 0 1 2 0 0 1 1 4 1 0 1 0 8 0 1 1 0 reserved 0 1 1 1 1 1 1 2 4 8 reserved interleave 0 0 0 normal mode m7 0 0 m8 m9 0 0 0 m11 m10 0 sequential reserved reserved reserved reserved reserved reserved full page* ) reserved * ) optional 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 sequential burst addressing interleave burst addressing 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6
hyb 39s16160ct-5.5/-6/-7 16-mbit synchronous dram data book 9 09.99 read and write access mode when ras is low and both cas and we are high at the positive edge of the clock, a ras cycle starts. according to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the word line are fired. a cas cycle is triggered by setting ras high and cas low at a clock timing after a necessary delay, t rcd , from the ras timing. we is used to define either a read (we = h) or a write (we = l) at this stage. sdram provides a wide variety of fast access modes. in a single cas cycle, serial data read or write operations are allowed at up to a 183 mhz data rate. the number of serial data bits is determined by the burst length programmed at the mode set operation; that is, either 1, 2, 4, 8, or full page (note that full page is an optional feature in this device). column addresses are segmented by the burst length and serial data accesses are done within this boundary. the first column address to be accessed is supplied at the cas timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence. for example, in a burst length of 8 with interleave sequence, if the first address is 2, then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5. full page burst operation is only possible using the sequential burst type and page length is a function of the i/o organization and column addressing. full page burst operation do not self terminate once the burst length has been reached. in other words, unlike burst length of 2, 3, or 8, full page burst continues until it is terminated using another command. similar to the page mode of conventional drams, burst read or write accesses on any column address are possible once the ras cycle latches sense amplifiers. the maximum refresh interval time ( t ras ) limits the number of random column accesses. a new burst access can be done even before the previous burst ends. the interrupt operation at every clock cycles is supported. when the previous burst is interrupted, the remaining addresses are overwritten by the new address with the full burst length. an interrupt which accompanies with an operation change from a read to a write is possible by exploiting dqm to avoid bus contention. when two banks are activated sequentially, interleaved bank read or write operations are possible. using the programmed burst length, alternate access and precharge operations on two banks can implement fast serial data access modes among many different pages. after two banks are activated, column to column interleave operation can be done between two different pages. refresh mode sdram has two refresh modes: cas before ras (cbr) automatic refresh and a self refresh. all of banks must be precharged before applying any refresh mode. an on-chip address counter increments the word and the bank addresses and no bank information is required for both refresh modes. the chip enters the automatic refresh mode, when ras and cas are held low and cke and we are held high at a clock timing. the mode restores word line after the refresh and no external precharge command is necessary. a minimum t rc time is required between two automatic refreshes in a burst refresh mode. the same rule applies to any access command after the automatic refresh operation. the chip has an on-chip timer and the self refresh mode is available. it enters the mode when ras , cas , and cke are low and we is high at a clock timing. all of external control signals including the clock are disabled. returning cke to high enables the clock and initiates the refresh exit operation. after the exit command, at least one t rc delay is required prior to any access command.
hyb 39s16160ct-5.5/-6/-7 16-mbit synchronous dram data book 10 09.99 dqm function dqm has two functions for data i/o read write operations. during reads, when it turns to high at a clock timing, data outputs are disabled and become high impedance after a two-clock delay (dqm data disable latency t dqz ). dqm also provides a data mask function for writes. when it is activated, the write operation at the next clock is prohibited (dqm write mask latency t dqw = zero clocks). suspend mode during normal access mode, cke is held high and clk is enabled. when cke is low, it freezes the internal clock and extends data read and write operations. one clock delay is required for mode entry and exit (clock suspend latency t csl ). power down to reduce standby power consumption, a power down mode is available. bringing cke low enters the power down mode and all of receiver circuits are gated. all banks must be precharged before entering this mode. one clock delay is required for mode entry and exit. the power down mode does not perform any refresh operations. auto precharge two methods are available to precharge sdrams. in an automatic precharge mode, the cas timing accepts one extra address, ca10, to determine whether the chip restores or not after the operation. if ca10 is high when a read command is issued, the read with auto-precharge function is initiated. if ca10 is high when a write command is issued, the write with auto-precharge function is initiated. the sdram automatically enters the precharge operation a time equal to t wr (write recovery time) after the last data in. precharge command if ca10 is low, the chip needs another way to precharge. in this mode, a separate precharge command is necessary. when ras and we are low and cas is high at a clock timing, it triggers the precharge operation. two address bits, a10 and a11, are used to define banks as shown in the following list. the precharge command may be applied coincident with the last of burst reads for cas latency = 1 and with the second to the last read data for cas latencies = 2 & 3. writes require a time t wr from the last burst data to apply the precharge command. burst termination after a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. these methods include using another read or write command to interrupt an existing burst operation, using a precharge command to interrupt a burst bank selection by address bits a10 a11 bank a only low low bank b only low high both a and b high dont care
hyb 39s16160ct-5.5/-6/-7 16-mbit synchronous dram data book 11 09.99 cycle and close the active bank, or using the burst stop command to terminate the existing burst operation but leave the bank open for future read or write commands to the same page of the active bank. when interrupting a burst with another read or write command, care must be taken to avoid dq contention. the burst stop command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. if a burst stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. data that is presented on the dq pins before the burst stop command is registered will be written to the memory. power up procedure all v dd and v ddq must reach the specified voltage no later than any of input signal voltages. an initial pause of 200 m s is required after power on. during this time, cke must be stable high and no self refresh command may be issued. all banks must be precharged and a minimum of eight auto refresh cycles are required prior to the mode register set operation.
hyb 39s16160ct-5.5/-6/-7 16-mbit synchronous dram data book 12 09.99 electrical characteristics absolute maximum ratings operating temperature range .......................................................................................0 to + 70 c storage temperature range .................................................................................. C 55 to + 150 c input/output voltage......................................................................... C 0.5 to min ( v dd + 0.5, 4.6) v power supply voltage v dd / v ddq .............................................................................. C 1.0 to + 4.6 v power dissipation .............................................................................................................. ......... 1 w data out current (short circuit)............................................................................................... 50 ma note: stresses above those listed under absolute maximum ratings may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. notes 1. all voltages are referenced to v ss 2. v ih may overshoot to v dd + 2.0 v for pulse width of < 4 ns with 3.3 v. v il may undershoot to C 2.0 v for pulse width < 4.0 ns with 3.3 v. pulse width measured at 50% with amplitude measured peak to dc reference. recommended operation and dc characteristics t a = 0 to 70 c; v ss = 0 v; v dd , v ddq = 3.3 v 0.3 v parameter symbol limit values unit notes min. max. input high voltage v ih 2.0 v dd +0.3 v 1, 2, 3 input low voltage v il C0.3 0.8 v 1, 2, 3 output high voltage ( i out =C2.0ma) v oh 2.4 C v 3 output low voltage ( i out =2.0ma) v ol C0.4v 3 input leakage current, any input (0 v < v in < v ddq , all other inputs = 0 v) i i(l) C5 5 m aC output leakage current (dq is disabled, 0 v < v out < v dd ) i o(l) C5 5 m aC
hyb 39s16160ct-5.5/-6/-7 16-mbit synchronous dram data book 13 09.99 capacitance t a = 0 to 70 c; v dd = 3.3 v 0.3 v, f = 1 mhz parameter symbol values unit min. max. input capacitance (clk) c i1 2.5 4.0 pf input capacitance (a0 - a12, ba0, ba1, ras , cas , we , cs , cke, dqm, udqm, ldqm) c i2 2.5 5.0 pf input/output capacitance (dq) c io 4.0 6.5 pf operating currents t a = 0 to 70 c, v dd = 3.3 v 0.3 v (recommended operating conditions unless otherwise noted) parameter & test condition symb.-5.5-6-7unitnote max. operating current burst length = 4 t rc 3 t rc(min.) , t ck 3 t ck(min.) , i o =0ma 2 bank interleave operation i cc1 110 100 90 ma 1, 2 precharge standby current in power down mode cke v il(max.) t ck 3 t ck(min.) i cc2p 22 2ma 2 cke v il(max.) , t ck = infinite i cc2ps 111ma C precharge standby current in non-power down mode cke 3 v ih(min.) t ck 3 t ck(min.) , input signals changed once in 3 cycles i cc2n 15 15 15 ma cs = high cke 3 v ih(min.) , t ck = infinite, input signals are stable i cc2ns 555maC active standby current in power down mode cke v il(max.) , t ck = t ck(min.) i cc3p 444maC cke v il(max.) , t ck =infinite, input signals are stable i cc3ps 444maC active standby current in non power down mode cke 3 v ih(min.) , t ck 3 t ck(min.) changed once in 3 cycles i cc3n 25 25 25 ma cs = high, 1 cke 3 v ih(min.) , t ck = infinite, input signals are stable i cc3ns 15 15 15 ma C burst operating current burst length = full page t rc = infinite t ck 3 t ck(min.) , i o =0ma, 2 banks interleave i cc4 1009080ma 1, 2
hyb 39s16160ct-5.5/-6/-7 16-mbit synchronous dram data book 14 09.99 notes 1. the specified values are valid when addresses are changed no more than three times during t rc(min.) and when no operation commands are registered on every rising clock edge during t rc(min.) . 2. the specified values are valid when data inputs (dqs) are stable during t rc(min.) . auto (cbr) refresh current t rc = t rc(min.) i cc5 70 60 50 ma 1, 2 self refresh cke 0.2 v i cc6 111ma 1, 2 operating currents (contd) t a = 0 to 70 c, v dd = 3.3 v 0.3 v (recommended operating conditions unless otherwise noted) parameter & test condition symb.-5.5-6-7unitnote max.
hyb 39s16160ct-5.5/-6/-7 16-mbit synchronous dram data book 15 09.99 ac characteristics 1, 2 t a = 0 to 70 c; v ss = 0 v; v dd = 3.3 v 0.3 v, t t = 1 ns parameter symb. limit values unit note -5.5 -6 -7 min. max. min. max. min. max. clock and clock enable clock cycle time cas latency = 3 cas latency = 2 t ck t ck 5.5 7.5 C C 6 8 C C 7 9 C C ns ns C clock frequency cas latency = 3 cas latency = 2 t ck t ck C C 183 133 C C 166 125 C C 143 115 mhz mhz C access time from clock cas latency = 3 cas latency = 2 t ac t ac C C 4.5 5.4 C C 5 6 C C 5 6 ns ns 2 3 clock high pulse width t ch 2C2C2.5CnsC clock low pulse width t cl 2C2C2.5CnsC transition time t t 0.5 10 0.5 10 0.5 10 ns C setup and hold times input setup time t is 1.5C2C2Cns 4 input hold time t ih 1C1C1Cns 4 cke setup time t cks 1.5C2C2Cns 4 cke hold time t ckh 1C1C1Cns 4 mode register set-up time t rsc 11 C 12 C 24 C ns C power down mode entry time t sb 05.50607nsC common parameters row to column delay time t rcd 15 C 16 C 18 C ns 5 row precharge time t rp 15 C 16 C 18 C ns 5 row active time t ras 33 C 36 100k 42 100k ns 5 row cycle time t rc 49.5 C 54 C 63 C ns 5 activate(a) to activate(b) command period t rrd 11 C 12 C 14 C ns C cas (a) to cas (b) command period t ccd 1C1C1CclkC
hyb 39s16160ct-5.5/-6/-7 16-mbit synchronous dram data book 16 09.99 refresh cycle refresh period (4096 cycles) t ref C64C64C64msC self refresh exit time t srex 10C1010ns 6 read cycle data out hold time t oh 2C2C2.5Cns 2 data out to low impedance time t lz 0C0C0CnsC data out to high impedance time t hz 25.52627nsC dqm data out disable latency t dqz C2C2C2clkC write cycle write recovery time t wr 2C2C2CclkC dqm write mask latency t dqw 0C0C0CclkC write latency t wl 0C0C0CclkC ac characteristics (contd) 1, 2 t a = 0 to 70 c; v ss = 0 v; v dd = 3.3 v 0.3 v, t t = 1 ns parameter symb. limit values unit note -5.5 -6 -7 min. max. min. max. min. max.
hyb 39s16160ct-5.5/-6/-7 16-mbit synchronous dram data book 17 09.99 notes for ac parameters: 1. for proper power-up see the operation section of this data sheet. 2. ac timing tests for lv-ttl versions have v il = 0.4 v and v ih = 2.4 v with the timing referenced to the 1.4 v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t = 1 ns with the ac output load circuit shown in figure below. specified t ac and t oh parameters are measured with a 30 pf only, without any resistive termination and with a input signal of 1 v/ns edge rate between 0.8 v and 2.0 v. 3. if clock rising time is longer than 1ns, a time ( t t /2 - 0.5) ns has to be added to this parameter. 4. if t t is longer than 1 ns, a time ( t t - 1) ns has to be added to this parameter. 5. these parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycle = specified value of timing period (counted in fractions as a whole number) 6. self refresh exit is a synchronous operation and begins on the 2nd positive clock edge after cke returns high. self refresh exit is not complete until a time period equal to t rc is satisfied once the self refresh exit command is registered. spt03404 clock 2.4 v 0.4 v input hold t setup t t t output 1.4 v t lz ac t t ac oh t hz t 1.4 v cl t ch t 30 pf i/o measurement conditions for t ac and t oh
hyb 39s16160ct-5.5/-6/-7 16-mbit synchronous dram data book 18 09.99 frequency vs. ac parameter relationship table cl t rcd t rp t rc t ras t rrd t ccd wl t wr -5.5 -parts 183 mhz 333962102 133 mhz 222752102 -6 -parts 166 mhz 333962102 125 mhz 222752102 -7 -parts 143 mhz 333962102 115 mhz 222752102
hyb 39s16160ct-5.5/-6/-7 16-mbit synchronous dram data book 19 09.99 package outlines gpx05956 125 26 50 20.95 0.13 1) 0.8 0.1 0.05 1.2 max. 10.16 0.13 11.76 0.2 1 0.05 0.1 0.2 50x m 0.1 0.05 + 0.4 index marking 1) does not include plastic or metal protrusion of 0.25 max. per side 0.15 + 0.06 0.03 0.1 0.5 - - plastic package, p-tsopii-50 ( 400 mil, 0.8 mm lead pitch ) thin small outline package, smd sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device

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